NVIDIA's next GeForce refresh just slipped off the calendar, and a hobbyist proved a full 3D rendering pipeline fits on a few hundred thousand transistors. One story is about GPU economics, the other about how little silicon a GPU actually needs to qualify as one.
RTX 50 Super Refresh Pushed to CES 2027
NVIDIA has told board partners to shelve the GeForce RTX 50 SUPER refresh until early 2027, according to leaker BenchLife's reporting relayed by VideoCardz (reported, not confirmed by NVIDIA). At least one partner already has finished RTX 50 SUPER hardware in hand, per VideoCardz's earlier report on the hold, which points to memory pricing rather than silicon readiness as the blocker.
The rumored lineup, an RTX 5080 SUPER at 24GB, RTX 5070 Ti SUPER at 24GB, and RTX 5070 SUPER at 18GB, needs the higher-density 3GB GDDR7 modules to hit those capacities without adding more chips to the board. VideoCardz's sourcing puts those 3GB modules at roughly $60 to $70 each against about $20 for a standard 2GB module, a cost jump steep enough to justify holding finished cards rather than shipping at a loss or repricing around it. PC Gamer's coverage of the broader 2026 GPU drought frames the delay as part of a thinner year for new cards generally, not an isolated SUPER-series problem.
For anyone holding off on an RTX 5000-series purchase hoping a refresh resets prices, the practical read is: plan around no new xx70/xx80 SUPER options before CES 2027, and current-generation pricing won't see relief from a refresh launch anytime soon.
A 240,000-Transistor Chip Renders Real 3D
A hobbyist FPGA designer's TinyGPU v2.0 came back from fabrication as working silicon rather than a simulation, Tom's Hardware reports. Designer Pongsagon Vichit built a rasterization and transform-and-lighting pipeline, backface culling, flat shading, one dynamic light, and a depth buffer, all inside roughly 200,000 to 240,000 transistors (sources differ on the exact count) fabricated through Tiny Tapeout's SKY25b shared-wafer shuttle, a service that splits ASIC fabrication costs across many small hobbyist and research designs on one wafer run.
The fabricated chip renders up to 1,000 triangles at 320×240 in 4-bit color, hitting about 6.5 fps at that load, roughly matching rather than beating its own FPGA prototype's 7.5 to 15 fps range. That is not a meaningful frame rate by any modern standard, and set against the tens of billions of transistors in a current RTX die it is closer to a teaching exercise than a preview of anything shippable. Vichit already has a v3.0 design queued for later in 2026.
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